Combined filter and transconductance amplifier

ABSTRACT

Embodiments of circuitry, which includes an operational transconductance amplifier and a passive circuit, are disclosed. The passive circuit is coupled to the operational transconductance amplifier. Further, the passive circuit receives an input signal and the operational transconductance amplifier provides an output current, such that the passive circuit and the OTA high-pass filter and integrate the input signal to provide the output signal.

RELATED APPLICATIONS

This application claims the benefit of U.S. provisional patent application No. 61/544,051, filed Oct. 6, 2011, the disclosure of which is incorporated herein by reference in its entirety.

FIELD OF THE DISCLOSURE

The present disclosure relates to operational transconductance amplifiers (OTAs) and circuits that incorporate OTAs.

BACKGROUND

FIG. 1A shows a prior art operational transconductance amplifier (OTA) 10 according to the prior art. The prior art OTA 10 receives a positive-side input voltage VP at a non-inverting input to the prior art OTA 10. Further, the prior art OTA 10 receives a negative-side input voltage VN at an inverting input to the prior art OTA 10. The prior art OTA 10 provides an output current IO based on a voltage difference between the positive-side input voltage VP and the negative-side input voltage VN. Specifically, the voltage difference is equal to a magnitude of the positive-side input voltage VP minus a magnitude of the negative-side input voltage VN. In this regard, since the prior art OTA 10 provides the output current IO based on the voltage difference, the prior art OTA 10 functions as a transconductance amplifier. As such, a transconductance GM of the prior art OTA 10 is equal to a magnitude of the output current IO divided by the voltage difference. Additionally, the prior art OTA 10 receives a first DC source signal DC1 and a second DC source signal DC2 to provide power to the prior art OTA 10.

FIG. 1B shows the prior art OTA 10 and a prior art OTA load circuit 12 according to the prior art. The prior art OTA load circuit 12 is coupled between an output from the prior art OTA 10 and a ground. The prior art OTA load circuit 12 has a load impedance ZL. The prior art OTA load circuit 12 receives the output current IO, such that an output voltage VO from the prior art OTA 10 is developed across the prior art OTA load circuit 12. In this regard, a magnitude of the output voltage VO is equal to the magnitude of the output current IO times a magnitude of the load impedance ZL. Since the prior art OTA 10 is an operational amplifier, the prior art OTA 10 may have very high input impedances and an open-circuit transconductance of the prior art OTA 10 may be very high. Therefore, the prior art OTA 10 may combine the functionality of an operational amplifier with transconductance characteristics, which may be useful in certain applications.

SUMMARY

Embodiments of the present disclosure relate to circuitry, which includes an operational transconductance amplifier (OTA) and a passive circuit. The passive circuit is coupled to the OTA. Further, the passive circuit receives an input signal and the OTA provides an output current, such that the passive circuit and the OTA high-pass filter and integrate the input signal to provide the output current.

In one embodiment of the OTA, the OTA and the passive circuit provide a combined filter and OTA. Further, the OTA is a single OTA. By combining high-pass filter, integrator, and transconductance functions using a single OTA, the combined filter and OTA may operate with a higher bandwidth than if multiple OTAs were used. As a result, for a given process technology, a bandwidth of the combined filter and OTA may be maximized, thereby maximizing an allowable bandwidth of the input signal.

Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

FIG. 1A shows a prior art operational transconductance amplifier (OTA) according to the prior art.

FIG. 1B shows the prior art OTA and a prior art OTA load circuit according to the prior art.

FIG. 2 shows details of circuitry according to one embodiment of the circuitry.

FIG. 3 shows details of a combined filter and OTA illustrated in FIG. 2 according to one embodiment of the combined filter and OTA.

FIG. 4 shows details of the combined filter and OTA illustrated in FIG. 2 according to an alternate embodiment of the combined filter and OTA.

FIG. 5 shows details of the combined filter and OTA illustrated in FIG. 2 according to an additional embodiment of the combined filter and OTA.

FIG. 6 shows details of the combined filter and OTA illustrated in FIG. 5 operating under a first set of operating conditions according to one embodiment of the combined filter and OTA.

FIG. 7 shows details of the combined filter and OTA illustrated in FIG. 5 operating under a second set of operating conditions according to one embodiment of the combined filter and OTA.

FIG. 8 shows details of the combined filter and OTA illustrated in FIG. 2 according to a further embodiment of the combined filter and OTA.

FIG. 9 shows the circuitry according to one embodiment of the circuitry.

FIG. 10 shows the circuitry according to an alternate embodiment of the circuitry.

FIG. 11 shows details of an envelope tracking power supply illustrated in FIG. 9 according to one embodiment of the envelope tracking power supply.

FIG. 12 shows details of the circuitry according to one embodiment of the circuitry.

FIG. 13 shows details of the envelope tracking power supply illustrated in FIG. 11 according to one embodiment of the envelope tracking power supply.

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

FIG. 2 shows details of circuitry 14 according to one embodiment of the circuitry 14. The circuitry 14 includes a combined filter and operational transconductance amplifier (OTA) 16, which includes an OTA 18 and a passive circuit 20. As such, the OTA 18 and the passive circuit 20 provide the combined filter and OTA 16. The OTA 18 is coupled to the passive circuit 20. Specifically, an inverting input to the OTA 18, a non-inverting input to the OTA 18, and an output from the OTA 18 are coupled to the passive circuit 20. The passive circuit 20 receives an input signal INS via an input IN and the OTA 18 provides an output current IO, such that the passive circuit 20 and the OTA 18 high-pass filter and integrate the input signal INS to provide the output current IO. A portion of the output current IO is fed back to the passive circuit 20. A feedback current IF is the portion of the output current IO that is fed back to the passive circuit 20. In one embodiment of the passive circuit 20, the passive circuit 20 does not include any active elements. In this regard, the input signal INS is received via the passive circuit 20 and the output current IO is provided via the OTA 18. The input signal INS is high-pass filtered and integrated to provide the output current IO using the passive circuit 20 and the OTA 18.

In one embodiment of the combined filter and OTA 16, the OTA 18 is a single OTA. By combining high-pass filter, integrator, and transconductance functions using the single OTA, the combined filter and OTA 16 may operate with a higher bandwidth than if multiple OTAs were used. As a result, for a given process technology, a bandwidth of the combined filter and OTA 16 may be maximized, thereby maximizing an allowable bandwidth of the input signal INS. The OTA 18 receives a positive-side input voltage VP at the non-inverting input to the OTA 18. Further, the OTA 18 receives a negative-side input voltage VN at the inverting input to the OTA 18. The OTA 18 provides the output current IO based on a voltage difference between the positive-side input voltage VP and the negative-side input voltage VN. Specifically, the voltage difference is equal to a magnitude of the positive-side input voltage VP minus a magnitude of the negative-side input voltage VN. In this regard, since the OTA 18 provides the output current IO based on the voltage difference, the OTA 18 functions as a transconductance amplifier. As such, a transconductance GM of the OTA 18 is equal to a magnitude of the output current IO divided by the voltage difference. Additionally, the OTA 18 receives a first DC source signal DC1 and a second DC source signal DC2 to provide power to the OTA 18.

FIG. 3 shows details of the combined filter and OTA 16 illustrated in FIG. 2 according to one embodiment of the combined filter and OTA 16. The combined filter and OTA 16 illustrated in FIG. 3 is similar to the combined filter and OTA 16 illustrated in FIG. 2, except the combined filter and OTA 16 illustrated in FIG. 3 shows details of the passive circuit 20. Specifically, the passive circuit 20 includes an OTA load circuit 22, a feedback impedance circuit 24, a shunt impedance circuit 26, a negative-side impedance circuit 28, a low-pass filter 30, and a positive-side impedance circuit 32. The OTA load circuit 22 is coupled between an output from the OTA 18 and a ground. The feedback impedance circuit 24 is coupled between the output from the OTA 18 and the inverting input to the OTA 18. The shunt impedance circuit 26 is coupled between the non-inverting input to the OTA 18 and the ground. The negative-side impedance circuit 28 is coupled between the inverting input to the OTA 18 and the input IN. A first end of the low-pass filter 30 is coupled to the input IN. The positive-side impedance circuit 32 is coupled between a second end of the low-pass filter 30 and the non-inverting input to the OTA 18.

The OTA load circuit 22 has a load impedance ZL. The OTA load circuit 22 receives a load current IL, such that an output voltage VO from the OTA 18 is developed across the OTA load circuit 22. In this regard, a magnitude of the output voltage VO is equal to the magnitude of the load current IL times a magnitude of the load impedance ZL. Since the OTA 18 is an operational amplifier, the OTA 18 may have very high input impedances and an open-circuit transconductance of the OTA 18 may be very high. Therefore, the OTA 18 may combine the functionality of an operational amplifier with transconductance characteristics. A magnitude of the output current IO is about equal to a sum of a magnitude of the load current IL and a magnitude of the feedback current IF. In one embodiment of the combined filter and OTA 16, the feedback current IF is much less than the load current IL. As such, the load current IL may be about equal to the output current IO. In this regard, the magnitude of the output voltage VO is about equal to a magnitude of the output current IO times the magnitude of the load impedance ZL. In one embodiment of the combined filter and OTA 16, a magnitude of the output current IO is at least ten times greater than a magnitude of the feedback current IF.

The feedback impedance circuit 24 has a feedback impedance ZF. The shunt impedance circuit 26 has a shunt impedance ZS. The negative-side impedance circuit 28 has a negative-side impedance ZN. The positive-side impedance circuit 32 has a positive-side impedance ZP. The input signal INS has an input voltage VI. During a first set of operating conditions, a frequency of the input signal INS is significantly less than a cutoff frequency of the low-pass filter 30. During a second set of operating conditions, the frequency of the input signal INS is significantly greater than the cutoff frequency of the low-pass filter 30. As such, during the first set of operating conditions, the low-pass filter 30 substantially passes the input signal INS to the positive-side impedance circuit 32. Further, during the first set of operating conditions, the low-pass filter 30 presents a low-pass filter resistance RLP between the input IN and the positive-side impedance circuit 32. During the second set of operating conditions, the low-pass filter 30 substantially blocks the input signal INS from the positive-side impedance circuit 32. Further, during the second set of operating conditions, the low-pass filter 30 presents approximately a short circuit to ground to the positive-side impedance circuit 32.

In one embodiment of the passive circuit 20, during the first set of operating conditions, a magnitude of the negative-side impedance ZN is about equal to a sum of a magnitude of the positive-side impedance ZP and a magnitude of the low-pass filter resistance RLP. Further, during the first set of operating conditions, a magnitude of the feedback impedance ZF is about equal to a magnitude of the shunt impedance ZS. The shunt impedance circuit 26, the low-pass filter 30, and the positive-side impedance circuit 32 form a positive-side voltage divider, such that the positive-side input voltage VP is equal to the input voltage VI divided down by the positive-side voltage divider. Further, the feedback impedance circuit 24 and the negative-side impedance circuit 28 form a negative-side voltage divider, such that the negative-side input voltage VN is equal to the input voltage VI divided down by the negative-side voltage divider.

During the first set of operating conditions, the negative-side voltage divider is about equal to the positive-side voltage divider. Further, since the OTA 18 drives the output current IO to make the negative-side input voltage VN about equal to the positive-side input voltage VP, a magnitude of the output voltage VO is driven to be about equal to ground. Therefore, during the first set of operating conditions, the input signal INS is blocked and the combined filter and OTA 16 behaves as a high-pass filter.

During the second set of operating conditions, since the low-pass filter 30 presents approximately a short circuit to ground to the positive-side impedance circuit 32, a magnitude of the positive-side input voltage VP is about equal to ground. Since the OTA 18 drives the output current IO to make the negative-side input voltage VN about equal to the positive-side input voltage VP, a magnitude of the output voltage VO is driven based on the input voltage VI and a gain determined by the feedback impedance ZF and the negative-side impedance ZN. Therefore, during the second set of operating conditions, the input signal INS is amplified and the combined filter and OTA 16 behaves as a high-pass filter. In general, the output current IO is further based on low-pass filtering the input signal INS. As such, in one embodiment of the combined filter and OTA 16, a cutoff frequency of the high-pass filter as provided by the combined filter and OTA 16 is equal to the cutoff frequency of the low-pass filter 30.

In one embodiment of the combined filter and OTA 16, during the second set of operating conditions, the frequency of the input signal INS is greater than the cutoff frequency of the high-pass filter as provided by the combined filter and OTA 16. In an alternate embodiment of the combined filter and OTA 16, during the second set of operating conditions, the frequency of the input signal INS is equal to at least two times the cutoff frequency of the high-pass filter as provided by the combined filter and OTA 16. In an additional embodiment of the combined filter and OTA 16, during the second set of operating conditions, the frequency of the input signal INS is equal to at least three times the cutoff frequency of the high-pass filter as provided by the combined filter and OTA 16. In another embodiment of the combined filter and OTA 16, during the second set of operating conditions, the frequency of the input signal INS is equal to at least five times the cutoff frequency of the high-pass filter as provided by the combined filter and OTA 16. In a further embodiment of the combined filter and OTA 16, during the second set of operating conditions, the frequency of the input signal INS is equal to at least ten times the cutoff frequency of the high-pass filter as provided by the combined filter and OTA 16. In an extra embodiment of the combined filter and OTA 16, during the second set of operating conditions, the frequency of the input signal INS is less than 100 times the cutoff frequency of the high-pass filter as provided by the combined filter and OTA 16.

In one embodiment of the combined filter and OTA 16, during the first set of operating conditions, the frequency of the input signal INS is less than the cutoff frequency of the high-pass filter as provided by the combined filter and OTA 16. In an alternate embodiment of the combined filter and OTA 16, during the first set of operating conditions, the frequency of the input signal INS is less than one-half the cutoff frequency of the high-pass filter as provided by the combined filter and OTA 16. In an additional embodiment of the combined filter and OTA 16, during the first set of operating conditions, the frequency of the input signal INS is less than one-tenth the cutoff frequency of the high-pass filter as provided by the combined filter and OTA 16.

In one embodiment of the combined filter and OTA 16, the high-pass filter as provided by the combined filter and OTA 16 is a single-pole filter. In an alternate embodiment of the combined filter and OTA 16, the high-pass filter as provided by the combined filter and OTA 16 is a two-pole filter. In an additional embodiment of the combined filter and OTA 16, the high-pass filter as provided by the combined filter and OTA 16 is a three-pole filter. In another embodiment of the combined filter and OTA 16, the high-pass filter as provided by the combined filter and OTA 16 is a four-pole filter. In a further embodiment of the combined filter and OTA 16, the high-pass filter as provided by the combined filter and OTA 16 is a five-pole filter.

In one embodiment of the low-pass filter 30, the low-pass filter 30 is a single-pole filter. In an alternate embodiment of the low-pass filter 30, the low-pass filter 30 is a two-pole filter. In an additional embodiment of the low-pass filter 30, the low-pass filter 30 is a three-pole filter. In another embodiment of the low-pass filter 30, the low-pass filter 30 is a four-pole filter. In a further embodiment of the low-pass filter 30, the low-pass filter 30 is a five-pole filter.

In one embodiment of the combined filter and OTA 16, the cutoff frequency of the high-pass filter as provided by the combined filter and OTA 16 is greater than one megahertz. In an alternate embodiment of the combined filter and OTA 16, the cutoff frequency of the high-pass filter as provided by the combined filter and OTA 16 is greater than two megahertz. In an additional embodiment of the combined filter and OTA 16, the cutoff frequency of the high-pass filter as provided by the combined filter and OTA 16 is greater than five megahertz. In another embodiment of the combined filter and OTA 16, the cutoff frequency of the high-pass filter as provided by the combined filter and OTA 16 is greater than ten megahertz. In a further embodiment of the combined filter and OTA 16, the cutoff frequency of the high-pass filter as provided by the combined filter and OTA 16 is greater than fifty megahertz. In an exemplary embodiment of the combined filter and OTA 16, the cutoff frequency of the high-pass filter as provided by the combined filter and OTA 16 is equal to about six megahertz. In another exemplary embodiment of the combined filter and OTA 16, the cutoff frequency of the high-pass filter as provided by the combined filter and OTA 16 is equal to about sixty megahertz.

In one embodiment of the OTA 18, the OTA 18 provides a derived output current DIO. The derived output current DIO is based on the output current IO, such that the derived output current DIO is representative of the output current IO. In one embodiment of the derived output current DIO, the derived output current DIO is about proportional to the output current IO. In one embodiment of the derived output current DIO, the derived output current DIO is based on a mirror current of the output current IO. In one embodiment of the derived output current DIO, a magnitude of the derived output current DIO is about equal to a first current scaling factor times a magnitude of the output current IO. In one embodiment of the OTA 18, the derived output current DIO is programmable. As such, in one embodiment of the OTA 18, the first current scaling factor is programmable. In this regard, in one embodiment of the OTA 18, a magnitude of the derived output current DIO is programmable.

FIG. 4 shows details of the combined filter and OTA 16 illustrated in FIG. 2 according to an alternate embodiment of the combined filter and OTA 16. The combined filter and OTA 16 illustrated in FIG. 4 is similar to the combined filter and OTA 16 illustrated in FIG. 3, except in the combined filter and OTA 16 illustrated in FIG. 4, the OTA 18 further receives an OTA configuration signal OCS. In one embodiment of the OTA 18, the derived output current DIO is programmable, such that the derived output current DIO is based on the output current IO and the OTA configuration signal OCS. In one embodiment of the derived output current DIO, the magnitude of the derived output current DIO is about equal to the first current scaling factor times a magnitude of the output current IO, such that the first current scaling factor is based on the OTA configuration signal OCS.

FIG. 5 shows details of the combined filter and OTA 16 illustrated in FIG. 2 according to an additional embodiment of the combined filter and OTA 16. The combined filter and OTA 16 illustrated in FIG. 5 is similar to the combined filter and OTA 16 illustrated in FIG. 3, except the combined filter and OTA 16 illustrated in FIG. 5 shows details of the low-pass filter 30 illustrated in FIG. 3. The low-pass filter 30 includes a first resistive element R1, a second resistive element R2, a first capacitive element C1, and a second capacitive element C2. The first resistive element R1 is coupled between the input IN and a first end of the first capacitive element C1. The second resistive element R2 is coupled between the first end of the first capacitive element C1 and a first end of the second capacitive element C2. A second end of the first capacitive element C1 is coupled to the ground. A second end of the second capacitive element C2 is coupled to the ground. The first end of the second capacitive element C2 is further coupled to the positive-side impedance circuit 32. In this regard, the first resistive element R1, the second resistive element R2, the first capacitive element C1, and the second capacitive element C2 form a two-pole low-pass filter. Alternate embodiments of the low-pass filter 30 may have any number of poles.

FIG. 6 shows details of the combined filter and OTA 16 illustrated in FIG. 5 operating under the first set of operating conditions according to one embodiment of the combined filter and OTA 16. A gain G of the combined filter and OTA 16 is equal to a magnitude of the output voltage VO divided by a magnitude of the input voltage VI as shown in EQ. 1 below. G=VO/VI.   EQ. 1:

However, the output voltage VO is based on the positive-side input voltage VP and the negative-side input voltage VN, which are both based on the input voltage VI, the passive circuit 20, and feeding back the output voltage VO. During the first set of operating conditions, the frequency of the input signal INS is significantly less than the cutoff frequency of the low-pass filter 30. As such, the frequency of the input signal INS is significantly less than the cutoff frequency of the high-pass filter as provided by the combined filter and OTA 16. Therefore, the first capacitive element C1 and the second capacitive element C2 may substantially behave as open circuits as shown. As such, the impedance of the low-pass filter 30 is about equal to the combined series resistance of the first resistive element R1 and the second resistive element R2. This series resistance is represented as 2R.

In this regard, the first resistive element R1, the second resistive element R2, the positive-side impedance circuit 32, and the shunt impedance circuit 26 form a voltage divider between the input IN and the ground to feed the non-inverting input to the OTA 18. In one embodiment of the OTA 18, the OTA has very high input impedances and an open-circuit transconductance of the OTA 18 is very high. As such, the OTA 18 drives the output voltage VO to make the negative-side input voltage VN about equal to the positive-side input voltage VP, as shown in EQ. 2 below. Further, the voltage divider is based on the series resistance 2R, the positive-side impedance ZP, and the shunt impedance ZS as shown in EQ. 3 below. VN=VP.   EQ. 2: VP=VI(ZS/(ZS+ZP+2R)).   EQ. 3:

Further, the feedback current IF flows through both the feedback impedance circuit 24 and the negative-side impedance circuit 28. However, if the negative-side impedance ZN is about equal to a sum of the series resistance 2R and the positive-side impedance ZP, as shown in EQ. 4 below, then a magnitude of the feedback current IF is about equal to a magnitude of the current flowing through the positive-side impedance circuit 32 and is about equal to a magnitude of the current flowing through the shunt impedance circuit 26. Additionally, if the feedback impedance ZF is about equal to the shunt impedance ZS, as shown in EQ. 5 below, then the voltage drop across the feedback impedance circuit 24 is about equal to the voltage drop across the shunt impedance circuit 26, as shown in EQ. 6 below. ZN=ZP+2R.   EQ. 4: ZF=ZS.   EQ. 5: (VP−0)=(VN−VO)   EQ. 6:

However, substituting EQ. 2 into EQ. 6 and then solving for the output voltage VO indicates that the output voltage VO is equal to zero, as shown in EQ. 7 below. (VN−0)=(VN−VO), therefore, VO=0.   EQ. 7:

Finally, substituting EQ. 7 into EQ. 1 indicates that the gain G of the combined filter and OTA 16 is equal to zero when the frequency of the input signal INS is significantly less than the cutoff frequency of the high-pass filter as provided by the combined filter and OTA 16, as shown in EQ. 8 below. G=VO/VI=0/VI=0.   EQ. 8:

Therefore, during the first set of operating conditions, the input signal INS is blocked and the combined filter and OTA 16 behaves as a high-pass filter.

FIG. 7 shows details of the combined filter and OTA 16 illustrated in FIG. 5 operating under the second set of operating conditions according to one embodiment of combined filter and OTA 16. During the second set of operating conditions, the frequency of the input signal INS is significantly greater than the cutoff frequency of the low-pass filter 30. As such, the frequency of the input signal INS is significantly greater than the cutoff frequency of the high-pass filter as provided by the combined filter and OTA 16. Therefore, the first capacitive element C1 and the second capacitive element C2 may substantially behave as short circuits as shown. As such, the impedance of the low-pass filter 30 presented to the positive-side impedance circuit 32 is equal to about zero and shorted to ground, as shown. Therefore, the positive-side input voltage VP is about equal to ground. Since the negative-side input voltage VN is about equal to the positive-side input voltage VP, as shown in EQ. 2, the negative-side input voltage VN is about equal to ground.

Therefore, since the feedback current IF flows through both the feedback impedance circuit 24 and the negative-side impedance circuit 28, and since the OTA 18 drives the output voltage VO to make the negative-side input voltage VN about equal to the positive-side input voltage VP, the input voltage VI is across the negative-side impedance circuit 28 and the output voltage VO is across the feedback impedance circuit 24, as shown in EQ. 9 below. VI/ZN=−VO/ZF.   EQ. 9:

Substituting EQ. 9 into EQ. 1 indicates that the gain G of the combined filter and OTA 16 is equal to a negative ratio of a magnitude of the feedback impedance ZF divided by a magnitude of the negative-side impedance ZN when the frequency of the input signal INS is significantly greater than the cutoff frequency of the high-pass filter as provided by the combined filter and OTA 16, as shown in EQ. 10 below. Since the gain G is negative, the output voltage VO is phase-shifted from the input voltage VI by about 180 degrees. G=VO/VI=−ZF/ZN.   EQ. 10:

Therefore, during the second set of operating conditions, the input signal INS is allowed to pass and the combined filter and OTA 16 again behaves as a high-pass filter.

FIG. 8 shows details of the combined filter and OTA 16 illustrated in FIG. 2 according to a further embodiment of the combined filter and OTA 16. The combined filter and OTA 16 illustrated in FIG. 8 is similar to the combined filter and OTA 16 illustrated in FIG. 5, except the combined filter and OTA 16 illustrated in FIG. 8 shows details of the OTA load circuit 22, the feedback impedance circuit 24, the shunt impedance circuit 26, the negative-side impedance circuit 28, and the positive-side impedance circuit 32. Specifically, the OTA load circuit 22 includes a load capacitive element CO and a load resistive element RO. The feedback impedance circuit 24 includes a feedback capacitive element CF and a feedback resistive element RF. The shunt impedance circuit 26 includes a shunt capacitive element CS and a shunt resistive element RS. The negative-side impedance circuit 28 includes a negative-side capacitive element CN and a negative-side resistive element RN. The positive-side impedance circuit 32 includes a positive-side capacitive element CP and a positive-side resistive element RP.

The load capacitive element CO and the load resistive element RO are coupled in series between the output from the OTA 18 and the ground. The feedback capacitive element CF and the feedback resistive element RF are coupled in parallel with one another. As such, the feedback capacitive element CF is coupled between the output from the OTA 18 and the inverting input to the OTA 18, and the feedback resistive element RF is coupled between the output from the OTA 18 and the inverting input to the OTA 18. The shunt capacitive element CS and the shunt resistive element RS are coupled in parallel with one another. As such, the shunt capacitive element CS is coupled between the non-inverting input to the OTA 18 and the ground, and the shunt resistive element RS is coupled between the non-inverting input to the OTA 18 and the ground.

In one embodiment of the combined filter and OTA 16, during the first set of operating conditions, a magnitude of the feedback impedance ZF is about equal to a magnitude of the shunt impedance ZS. Therefore, during the first set of operating conditions, a resistance of the feedback resistive element RF is about equal to a resistance of the shunt resistive element RS. Further, a capacitance of the feedback capacitive element CF is about equal to a capacitance of the shunt capacitive element CS.

The negative-side capacitive element CN and the negative-side resistive element RN are coupled in series between the inverting input to the OTA 18 and the input IN. The positive-side capacitive element CP and the positive-side resistive element RP are coupled in series between the first end of the second capacitive element C2 and the non-inverting input to the OTA 18. In one embodiment of the combined filter and OTA 16, during the first set of operating conditions, a magnitude of the negative-side impedance ZN is about equal to a sum of a magnitude of the positive-side impedance ZP and a magnitude of the low-pass filter resistance RLP. Therefore, during the first set of operating conditions, a resistance of the negative-side resistive element RN is about equal to a sum of a resistance of the positive-side resistive element RP, a resistance of the first resistive element R1, and a resistance of the second resistive element R2. Further, during the first set of operating conditions, a capacitance of the negative-side capacitive element CN is about equal to a capacitance of the positive-side capacitive element CP.

In one embodiment of the combined filter and OTA 16, during the second set of operating conditions, the combined filter and OTA 16 behaves as a combined high-pass filter and integrator. In this regard, in one embodiment of the feedback impedance circuit 24 and the negative-side impedance circuit 28, during the second set of operating conditions, a resistance of the feedback resistive element RF is significantly larger than a capacitive reactance of the feedback capacitive element CF, a resistance of the negative-side resistive element RN is significantly larger than a capacitive reactance of the negative-side capacitive element CN, a resistance of the load resistive element RO is significantly larger than a capacitive reactance of the load capacitive element CO, and the capacitive reactance of the feedback capacitive element CF is significantly larger than the resistance of the load resistive element RO.

Therefore, the negative-side impedance ZN is mainly resistive, the feedback impedance ZF is mainly capacitive, the load impedance ZL is mainly resistive, and the feedback current IF is significantly less than the output current 10. Since the negative-side impedance ZN is mainly resistive and the feedback impedance ZF is mainly capacitive, the output voltage VO is approximately an integral of the input voltage VI. Further, since the feedback current IF is significantly less than the output current IO and since the load impedance ZL is mainly resistive, the output voltage VO and the output current IO are substantially phase-aligned. Therefore, the output current IO is an integral of the input voltage VI. Thus, the combined filter and OTA 16 behaves as a combined high-pass filter and integrator.

FIG. 9 shows the circuitry 14 according to one embodiment of the circuitry 14. The circuitry 14 further includes radio frequency (RF) transmitter circuitry 34, RF system control circuitry 36, RF front-end circuitry 38, an RF antenna 40, and a DC power source 42. The RF transmitter circuitry 34 includes transmitter control circuitry 44, an RF power amplifier (PA) 46, an envelope tracking power supply 48, and PA bias circuitry 50. The envelope tracking power supply 48 includes the combined filter and OTA 16 (FIG. 2). In this regard, in one embodiment of the circuitry 14, the circuitry 14 illustrated in FIG. 9 is an RF communications system.

In one embodiment of the circuitry 14, the RF front-end circuitry 38 receives via the RF antenna 40, processes, and forwards an RF receive signal RFR to the RF system control circuitry 36. The RF system control circuitry 36 provides an envelope power supply control signal VRMP and a transmitter configuration signal PACS to the transmitter control circuitry 44. The RF system control circuitry 36 provides an RF input signal RFI to the RF PA 46. The DC power source 42 provides a DC source signal VDC to the envelope tracking power supply 48. In one embodiment of the DC power source 42, the DC power source 42 is a battery.

The transmitter control circuitry 44 is coupled to the envelope tracking power supply 48 and to the PA bias circuitry 50. The envelope tracking power supply 48 provides an envelope power supply signal EPS to the RF PA 46 based on the envelope power supply control signal VRMP. The DC source signal VDC provides power to the envelope tracking power supply 48. As such, the envelope power supply signal EPS is based on the DC source signal VDC. The envelope power supply control signal VRMP is representative of a setpoint of the envelope power supply signal EPS. The RF PA 46 receives and amplifies the RF input signal RFI to provide an RF transmit signal RFT using the envelope power supply signal EPS. The envelope power supply signal EPS provides power for amplification. The RF front-end circuitry 38 receives, processes, and transmits the RF transmit signal RFT via the RF antenna 40. In one embodiment of the RF transmitter circuitry 34, the transmitter control circuitry 44 configures the RF transmitter circuitry 34 based on the transmitter configuration signal PACS.

The PA bias circuitry 50 provides a PA bias signal PAB to the RF PA 46. In this regard, the PA bias circuitry 50 biases the RF PA 46 via the PA bias signal PAB. In one embodiment of the PA bias circuitry 50, the PA bias circuitry 50 biases the RF PA 46 based on the transmitter configuration signal PACS. In one embodiment of the RF front-end circuitry 38, the RF front-end circuitry 38 includes at least one RF switch, at least one RF amplifier, at least one RF filter, at least one RF duplexer, at least one RF diplexer, at least one RF amplifier, the like, or any combination thereof. In one embodiment of the RF system control circuitry 36, the RF system control circuitry 36 is RF transceiver circuitry, which may include an RF transceiver IC, baseband controller circuitry, the like, or any combination thereof. In one embodiment of the RF transmitter circuitry 34, the envelope tracking power supply 48 provides the envelope power supply signal EPS, which has switching ripple. In one embodiment of the RF transmitter circuitry 34, the envelope power supply signal EPS provides power for amplification and envelope tracks the RF transmit signal RFT.

FIG. 10 shows the circuitry 14 according to an alternate embodiment of the circuitry 14. The circuitry 14 illustrated in FIG. 10 is similar to the circuitry 14 illustrated in FIG. 9, except in the circuitry 14 illustrated in FIG. 10, the RF transmitter circuitry 34 further includes a digital communications interface 52, which is coupled between the transmitter control circuitry 44 and a digital communications bus 54. The digital communications bus 54 is also coupled to the RF system control circuitry 36. As such, the RF system control circuitry 36 provides the envelope power supply control signal VRMP (FIG. 9) and the transmitter configuration signal PACS (FIG. 9) to the transmitter control circuitry 44 via the digital communications bus 54 and the digital communications interface 52.

FIG. 11 shows details of the envelope tracking power supply 48 illustrated in FIG. 9 according to one embodiment of the envelope tracking power supply 48. The envelope tracking power supply 48 includes power supply control circuitry 56, an analog supply 58, and a switching supply 60. The power supply control circuitry 56 controls the analog supply 58 and the switching supply 60. The analog supply 58 and the switching supply 60 provide the envelope power supply signal EPS, such that the analog supply 58 partially provides the envelope power supply signal EPS and the switching supply 60 partially provides the envelope power supply signal EPS. The switching supply 60 may provide power more efficiently than the analog supply 58. However, the analog supply 58 may provide the envelope power supply signal EPS more accurately than the switching supply 60. As such, the analog supply 58 regulates a voltage of the envelope power supply signal EPS based on the setpoint of the envelope power supply signal EPS, and the switching supply 60 operates to drive an output current from the analog supply 58 toward zero to maximize efficiency. In this regard, the analog supply 58 behaves like a voltage source and the switching supply 60 behaves like a current source.

FIG. 12 shows details of the circuitry 14 according to one embodiment of the circuitry 14. The circuitry 14 illustrated in FIG. 12 is similar to the circuitry 14 illustrated in FIG. 2, except in the circuitry 14 illustrated in FIG. 12, the OTA 18 further provide the derived output current DIO and a first current sense signal CS1, and receives the OTA configuration signal OCS. The first current sense signal CS1 is based on the derived output current DIO, such that the first current sense signal CS1 is representative of the derived output current DIO. In one embodiment of the first current sense signal CS1, the first current sense signal CS1 is about proportional to the derived output current DIO. In one embodiment of the first current sense signal CS1, the first current sense signal CS1 is based on a mirror current of the output current IO. In one embodiment of the first current sense signal CS1, a magnitude of the first current sense signal CS1 is about equal to a second current scaling factor times a magnitude of the derived output current DIO. In one embodiment of the OTA 18, the first current sense signal CS1 is programmable. As such, in one embodiment of the OTA 18, the second current scaling factor is programmable. In this regard, in one embodiment of the OTA 18, a magnitude of the first current sense signal CS1 is programmable. In one embodiment of the first current sense signal CS1, the first current sense signal CS1 is a voltage signal. In an alternate embodiment of the first current sense signal CS1, the first current sense signal CS1 is a current signal.

In one embodiment of the OTA 18, the derived output current DIO is programmable, such that the derived output current DIO is based on the output current IO and the OTA configuration signal OCS. In one embodiment of the derived output current DIO, the magnitude of the derived output current DIO is about equal to the first current scaling factor times a magnitude of the output current IO, such that the first current scaling factor is based on the OTA configuration signal OCS. In one embodiment of the OTA 18, the first current sense signal CS1 is programmable, such that the first current sense signal CS1 is based on the derived output current DIO and the OTA configuration signal OCS. In one embodiment of the first current sense signal CS1, the magnitude of the first current sense signal CS1 is about equal to the second current scaling factor times a magnitude of the derived output current DIO, such that the second current scaling factor is based on the OTA configuration signal OCS. In one embodiment of the OTA 18, both the first current scaling factor and the second current scaling factor are based on the OTA configuration signal OCS.

FIG. 13 shows details of the envelope tracking power supply 48 illustrated in FIG. 11 according to one embodiment of the envelope tracking power supply 48. The envelope tracking power supply 48 includes the power supply control circuitry 56, the analog supply 58, and the switching supply 60. The analog supply 58 includes an active ripple cancellation circuit 62, a parallel amplifier 64, and a parallel amplifier offset capacitive element CA. The switching supply 60 includes switching circuitry 66, a switching supply inductive element LW, and a switching supply capacitive element CW. The active ripple cancellation circuit 62 includes a delay circuit 68, the combined filter and OTA 16, and a ripple circuit offset capacitive element CR. The power supply control circuitry 56 receives the DC source signal VDC.

The parallel amplifier 64 is coupled to the power supply control circuitry 56 and is powered via the DC source signal VDC. The parallel amplifier offset capacitive element CA is coupled between the parallel amplifier 64 and the RF PA 46 (FIG. 11). During operation, the parallel amplifier offset capacitive element CA may have an offset voltage. This offset voltage may allow the parallel amplifier 64 to function properly even if a voltage of the envelope power supply signal EPS is greater than a voltage of the DC source signal VDC. The parallel amplifier 64 provides a second current sense signal CS2 to the switching circuitry 66. The second current sense signal CS2 is indicative of an output current from the parallel amplifier 64. In an alternate embodiment of the analog supply 58, the parallel amplifier offset capacitive element CA is omitted.

The power supply control circuitry 56 controls the parallel amplifier 64 and the switching circuitry 66. The parallel amplifier 64 and the switching supply 60 provide the envelope power supply signal EPS, such that the parallel amplifier 64 partially provides the envelope power supply signal EPS and the switching supply 60 partially provides the envelope power supply signal EPS. The switching supply 60 may provide power more efficiently than the parallel amplifier 64. However, the parallel amplifier 64 may provide the envelope power supply signal EPS more accurately than the switching supply 60. As such, the parallel amplifier 64 regulates the voltage of the envelope power supply signal EPS based on the setpoint of the envelope power supply signal EPS. The switching supply 60 operates to drive the output current from the analog supply 58 toward zero to maximize efficiency based on the second current sense signal CS2. In this regard, the parallel amplifier 64 behaves like a voltage source and the switching supply 60 behaves like a current source.

The switching circuitry 66 is coupled to the power supply control circuitry 56 and is powered via the DC source signal VDC. The switching supply inductive element LW is coupled between the switching circuitry 66 and the RF PA 46 (FIG. 11). The switching supply capacitive element CW is coupled between the RF PA 46 (FIG. 11) and the ground. The switching circuitry 66 provides an inductor input signal LIN to the switching supply inductive element LW and to the delay circuit 68. The switching supply inductive element LW has an inductor current IL. The envelope power supply signal EPS is at least partially based on the inductor current IL. A voltage of the inductor input signal LIN is a square wave signal. A voltage of the envelope power supply signal EPS is fairly smooth due to filtering by the switching supply capacitive element CW and voltage regulation by the parallel amplifier 64. In one embodiment of the combined filter and OTA 16, the cutoff frequency of the high-pass filter as provided by the combined filter and OTA 16 is about equal to a frequency of the inductor input signal LIN.

During a peak of the square wave signal, the voltage of the inductor input signal LIN is positive with respect to the voltage of the envelope power supply signal EPS, thereby causing the inductor current IL to increase. Conversely, during a valley of the square wave signal, the voltage of the inductor input signal LIN is negative with respect to the voltage of the envelope power supply signal EPS, thereby causing the inductor current IL to decrease. As a result, a square wave voltage is developed across the switching supply inductive element LW. Due to integration by the switching supply inductive element LW, this square wave voltage produces a triangular wave ripple current in the inductor current IL. This ripple current is undesirable and may be problematic for proper operation of the RF PA 46 (FIG. 11).

As such, the active ripple cancellation circuit 62 at least partially cancels the triangular wave ripple current by providing the derived output current

DIO, which is based on estimating the ripple current using the inductor input signal LIN. The derived output current DIO is an inverted estimated ripple current, which at least partially cancels the triangular wave ripple current in the inductor current IL.

Specifically, the delay circuit 68 is coupled between the switching circuitry 66 and the combined filter and OTA 16. The combined filter and OTA 16 is coupled between the delay circuit 68 and the ripple circuit offset capacitive element CR. The ripple circuit offset capacitive element CR is coupled between the combined filter and OTA 16 and the RF PA 46 (FIG. 11). In one embodiment of the combined filter and OTA 16, the combined filter and OTA 16 is the combined filter and OTA 16 illustrated in FIG. 12. As such, the combined filter and OTA 16 is coupled to the power supply control circuitry 56 and is powered via the DC source signal VDC. During operation, the ripple circuit offset capacitive element CR may have an offset voltage. This offset voltage may allow the combined filter and OTA 16 to function properly even if a voltage of the envelope power supply signal EPS is greater than a voltage of the DC source signal VDC. In an alternate embodiment of the active ripple cancellation circuit 62, the ripple circuit offset capacitive element CR is omitted. In one embodiment of the active ripple cancellation circuit 62, the derived output current DIO is fed between the parallel amplifier 64 and the parallel amplifier offset capacitive element CA.

The delay circuit 68 receives and delays the inductor input signal LIN to provide the input signal INS. Delaying the inductor input signal LIN may be needed to properly time-align the inverted estimated ripple current with the triangular wave ripple current. In one embodiment of the power supply control circuitry 56, the power supply control circuitry 56 feeds the OTA configuration signal OCS to the delay circuit 68. The power supply control circuitry 56 controls the delay of the delay circuit 68 via the OTA configuration signal OCS. The delay may be adjusted based on the envelope power supply control signal VRMP (FIG. 9). In another embodiment of the active ripple cancellation circuit 62, the delay circuit 68 is fed with an alternate version of the inductor input signal LIN, such as a buffered version of the inductor input signal LIN. In an alternate embodiment of the active ripple cancellation circuit 62, the delay circuit 68 is omitted. To provide the inverted estimated ripple current via the derived output current DIO, the combined filter and OTA 16 must high-pass filter the input signal INS to process only frequencies of the triangular wave ripple current. Further, the combined filter and OTA 16 must integrate the input signal INS to convert the square wave input signal INS into a triangular wave. Finally, the combined filter and OTA 16 must invert the high-pass filtered and integrated input signal INS, as previously shown in EQ. 10, to provide the derived output current DIO, which is the inverted estimated ripple current.

The power supply control circuitry 56 provides the OTA configuration signal OCS to the combined filter and OTA 16. As such, the power supply control circuitry 56 may configure the combined filter and OTA 16 as needed via the OTA configuration signal OCS. The combined filter and OTA 16 provides the first current sense signal CS1 to the switching circuitry 66 based on the derived output current DIO. As such, in one embodiment of the switching supply 60, the switching supply 60 operates to drive the output current from the analog supply 58 toward zero to maximize efficiency based on both the first current sense signal CS1 and the second current sense signal CS2.

Some of the circuitry previously described may use discrete circuitry, integrated circuitry, programmable circuitry, non-volatile circuitry, volatile circuitry, software executing instructions on computing hardware, firmware executing instructions on computing hardware, the like, or any combination thereof. The computing hardware may include mainframes, micro-processors, micro-controllers, DSPs, the like, or any combination thereof.

None of the embodiments of the present disclosure are intended to limit the scope of any other embodiment of the present disclosure. Any or all of any embodiment of the present disclosure may be combined with any or all of any other embodiment of the present disclosure to create new embodiments of the present disclosure.

Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow. 

What is claimed is:
 1. Circuitry comprising: a passive circuit adapted to receive an input signal; and an operational transconductance amplifier (OTA) coupled to the passive circuit and adapted to provide an output current, such that: the passive circuit and the OTA provide a high-pass filter, which is configured to high-pass filter and integrate the input signal to provide the output current; the passive circuit comprises a feedback impedance circuit coupled between an output from the OTA and an inverting input to the OTA; and during a first set of operating conditions, the feedback impedance circuit has a feedback current, such that a magnitude of the output current is at least ten times greater than a magnitude of the feedback current.
 2. The circuitry of claim 1 wherein the passive circuit does not comprise any active elements.
 3. The circuitry of claim 1 wherein the OTA is a single OTA.
 4. The circuitry of claim 1 wherein a cutoff frequency of the high-pass filter is greater than about one megahertz.
 5. The circuitry of claim 1 wherein a cutoff frequency of the high-pass filter is equal to about six megahertz.
 6. The circuitry of claim 1 wherein the high-pass filter is a two-pole filter.
 7. The circuitry of claim 1 wherein the passive circuit comprises a low-pass filter, such that the output current is further based on low-pass filtering the input signal.
 8. Circuitry comprising: a passive circuit adapted to receive an input signal; and an operational transconductance amplifier (OTA) coupled to the passive circuit and adapted to provide an output current, such that: the passive circuit and the OTA provide a high-pass filter, which is configured to high-pass filter and integrate the input signal to provide the output current; the passive circuit comprises a low-pass filter, such that the output current is further based on low-pass filtering the input signal; and a cutoff frequency of the high-pass filter is about equal to a cutoff frequency of the low-pass filter.
 9. The circuitry of claim 1 wherein: the passive circuit further comprises a shunt impedance circuit coupled between a non-inverting input to the OTA and a ground; during the first set of operating conditions, the feedback impedance circuit has a feedback impedance and the shunt impedance circuit has a shunt impedance; and the feedback impedance is about equal to the shunt impedance.
 10. The circuitry of claim 1 wherein the passive circuit further comprises a negative-side impedance circuit coupled between the inverting input to the OTA and an input, which is adapted to receive the input signal.
 11. The circuitry of claim 1 wherein the OTA is further adapted to provide a derived output current that is representative of the output current.
 12. The circuitry of claim 11 wherein a magnitude of the derived output current is programmable.
 13. The circuitry of claim 11 wherein the OTA is further adapted to provide a current sense signal that is representative of the derived output current.
 14. Circuitry comprising: an active ripple cancellation circuit and a switching supply inductive element; a passive circuit adapted to receive an input signal; and an operational transconductance amplifier (OTA) coupled to the passive circuit and adapted to provide an output current, such that: the passive circuit and the OTA high-pass filter and integrate the input signal to provide the output current; the OTA and the passive circuit provide a combined filter and OTA; the OTA is further adapted to provide a derived output current that is representative of the output current; the active ripple cancellation circuit comprises the combined filter and OTA; the switching supply inductive element has an inductor current having a ripple current; and the derived output current at least partially cancels the ripple current.
 15. The circuitry of claim 14 further comprising a radio frequency (RF) power amplifier (PA) wherein: the RF PA is adapted to receive and amplify an RF input signal to provide an RF transmit signal using an envelope power supply signal; and the envelope power supply signal is at least partially based on the inductor current.
 16. The circuitry of claim 14 further comprising switching circuitry wherein: the switching circuitry is adapted to provide an inductor input signal to the switching supply inductive element and the active ripple cancellation circuit; and the derived output current is based on the inductor input signal.
 17. The circuitry of claim 16 wherein: the active ripple cancellation circuit further comprises a delay circuit coupled between the switching circuitry and the combined filter and OTA; the delay circuit is adapted to receive the inductor input signal; and the delay circuit is further adapted to provide the input signal based on delaying the inductor input signal. 